1. Field of the Invention
The present invention relates to a write/precharge flag signal generation circuit of a semiconductor memory device and a circuit for driving a bitline isolation circuit in a sense amplifier using the same, and more particularly to, a circuit for driving a bitline isolation circuit, capable of efficiently isolating a connection between a bitline and the sense amplifier at the beginning of a read operation.
2. Discussion of Related Art
In general, data stored in a memory cell of a semiconductor memory device is amplified by a bitline sense amplifier. FIG. 6 is a circuit diagram illustrating a general bitline sense amplifier.
A sense amplifier 1 sensing data loaded in a pair of bitlines BL and /BL by sense amplifier control signals RTO and /S is comprised of first and second NMOS transistors NM1, NM2, and first and second PMOS transistors PM1, PM2, cross-coupled each other. A first isolation circuit 2 isolating or connecting between a pair of bitlines BL and /BL and the sense amplifier 1 by a bitline isolation signal BISH is comprised of third and fourth NMOS transistors NM3 and NM4. A second isolation circuit 3 isolating or connecting between the sense amplifier 1 and another bitline by a bitline isolation signal BISL is comprised of fifth and sixth NMOS transistors NM5 and NM6. A seventh NMOS transistor NM7 equalizes a pair of bitlines BL and /BL by a bitline equalization signal BLEQ. A precharge unit 4 is comprised of eighth and ninth NMOS transistors NM8 and NM9 precharging a pair of bitlines BL and /BL to a precharge voltage VBLP by the bitline equalization signal BLEQ. A connection unit 5 is comprised of tenth and eleventh NMOS transistors NM10 and NM11 alternatively transferring the data sensed by the sense amplifier 1 into input/output lines IO and /IO, according to a column control signal YI.
It will now be described about the operation of the general sense amplifier constructed as described above.
First of all, since a voltage of a word line in a standby state is a ground voltage and the bitline equalization signal BLEQ is a high level, a pair of bitlines BL and /BL have been precharged to an identical voltage VBLP, and the sense amplifier control signals RTO and /S have been all precharged to a precharge voltage VBLP.
Then, as the bitline equalization signal BLEQ becomes a low level, a pair of bitlines BL and /BL become a floating state isolated from the external, with maintaining the precharge voltage VBLP.
On the other hand, a row decoder selects one word line by decoding a row address inputted from the external and then rises its voltage. Accordingly, a charge of a cell connected to the selected word line is loaded on the corresponding bitline BL, and then rises or falls down the voltage of the bitline according to the data of the cell. During this, the sense amplifier 1 is activated and a voltage difference of a pair of bitlines BL and /BL is amplified by the sense amplifier control signals RTO and /S. When the voltage difference of a pair of bitlines BL and /BL are developed to a certain point, the sense amplifier 1 is disabled by the sense amplifier control signals RTO and /S and then the sensing operation is completed.
Here, the first isolation circuit 2 isolates a connection between a pair of bitlines and the sense amplifier in order to reduce load to be amplified by the sense amplifier at the beginning of sensing operation.
The first isolation circuit 2 is controlled by an isolation driving circuit shown in FIG. 1 and a control circuit shown in FIG. 2. It will be described about an operation of the isolation driving circuit with reference to FIGS. 1, 2 and 3 as follows.
At first, it will be described about the control circuit in FIG. 2.
A control signal write6 is initiated to a high level during a power up operation and then becomes a low level according to a read command, while becoming a high level according to a write command. A control signal wlst_bis becomes a high level during a row active operation, and then becomes a low level during a precharge operation.
During a read cycle in the row active operation, the control signal wlst_bis becomes a high level and the control signal write6 becomes a low level. As a result, an output bis_ctrl of a NAND gate G1 becomes a low level.
Referring to FIG. 1, a control signal sbe is a sensing start signal of the bitline sense amplifier. When the control signal sbe is in a high level, the sensing operation is started. Control signals bs_u, bs_d are block select signals and the signals are enabled in a low level.
As the output bis_ctrl of the control circuit in FIG. 2 is a low level, a NOR gate Nor1 inverts an inputted signal. When the control signal sbe is transited from a low level to a high level (starting sensing of the bitline sense amplifier), an output AA of a NAND gate nand1 becomes a low level so that an output of the NOR gate Nor1 becomes a high level. Accordingly, an output of a differential amplifier 10 becomes a low level so that an output node0 becomes a low level.
As soon as the output node0 becomes a low level, NAND gates nand2, nand4 output a high level regardless of the control signals bs_u and bs_d. Therefore, PMOS transistors P0 and P1 are turned off. In addition, as soon as the output node0 becomes a low level, NAND gates nand3 and nand5 output a high level regardless of the control signals bs_u and bs_d. Accordingly, outputs bsb_ud and bsb_dd becomes a high level. One of the control signals bs_u, bs_d becomes a low level in a row active state, so that an output of a NAND gate nand6 becomes high state. Therefore, PMOS transistors P2 and P3 are turned off. As a result, because the NMOS transistor n0 and n1 are turned on, the control signals BISH and BISL driving the first and second isolation circuits in FIG. 6 become a low level.
Then, when the output of the differential amplifier 10 is transited from a low level to a high level, that is, the output node0 is transited from a low level to a high level, the NAND gates nand2, nand3, nand4 and nand5 are all operated as an inverter. Assuming that the control signal bs_u is a low level and the control signal bs_d is a high level, as the PMOS transistor P0 is turned on and its output bis_ud is a high level, the NMOS transistor n1 is turned on but the PMOS transistor P1 and the NMOS transistor n0 are turned off. During this, the PMOS transistors P2 and P3 maintain a turn-off state. Therefore, the output BISH becomes VPP level, while the output BISL becomes a zero level.
The outputs BISH, BISL becomes inputs of the first and second isolation circuit of the bitline sense amplifier as shown in FIG. 6. There is a main characteristic operation of the conventional art to make the aforementioned output BISH with a low level at the beginning of sensing (the moment that a RTO of FIG. 6 moves to a high level and a /S of FIG. 6 moves to a low level) and then to make it with VPP level after a predetermined time.
Additionally, during a write cycle in the row active operation, the control signal write becomes a high level and then the output bis_ctrl of the control circuit becomes a high level. As a result, the output node0 becomes a high level. Accordingly, the outputs BISH, BISL don't become a low level at the beginning of sensing during the write operation. If the outputs BISH and BISL are off at the beginning of sensing during the write operation as during the read operation, in case that the off period and a period enabling the column select line YI of FIG. 6 are overlapped, the write operation is performed only in the sense amplifier 1 by transistors NM11 and NM12 in FIG. 6 but isn't performed in a memory cell connected to the bitline, during the column select line YI being enabled. As a result, the write operation of the memory cell is dependant on the sensing operation of the sense amplifier after closing the column select line YI, so that tWR (a time possible to get a precharge command after a write command) is being worse.
However, in the conventional art, if the read command is given after the row active as shown in FIG. 3, the timing that an output of the NAND gate nand1 is generated to a low level by transiting the control signal sbe to a high level may be later that the timing that the output bis_ctrl of the control circuit by the read command is transited to a low level. During this, an output of the NOR gate Nor1 is not generated to a high level, or if generated so, a pulse width is being narrower. That is, as shown in FIG. 3, the output node0 should maintain a low level width up to a section denoted with a dotted line but can have less row pulse width than that. In this case, it is disadvantageous not to maintain the BISH with a low level at the beginning of sensing for a predetermined time.